Verilator is used to allow the initial Forth image to compile its own initial software installation, which is then re-compiled into the design so the resulting FPGA runs whatever the application is from power up. An excellent and useful example of doing so is included in Swapforth, which is used when make -C j1a clean bootstrap is called. The commercial tools support both, even in the same project at once, on a module-by-module basis.Īnother very useful simulation tool (which also runs under Mac OS X, via a package in one-or-the-other of homebrew and macports) is Verilator, which allows for compilation of HDL into efficiently-running native binaries for the purposes of running entire SoC's in simulated form. If you are serious about learning HDL synthesis for FPGA's, you will probably have to eventually learn be at least passingly familiar with both Verilog and VHDL anyway.
It may well be worthwhile, if you are a beginner to FPGA design, starting with MyHDL (which is a python interface which can both simulate hardware, as well as auto-generate either VHDL or Verilog for FPGA synthesis), until you are familiar with HDL design, then drilling down into detail with VHDL and Verilog later. I have not actually ran one of those on Mac OS X, which is why this answer is Maybe. So, if you have your heart set on learning VHDL only, you will need a VHDL to Verilog converter, as VHDL isn't supported directly. Icestorm includes some simple examples which are suitable for an introduction to synthesis HDL for FPGA's, but these are in verilog, not VHDL. I have compiled and am able to run it natively under Mac OS X, although setting it up wasn't as trivial as doing the same under Linux.
Icestorm is an open source FPGA compilation toolchain for verilog on Lattice ice40 FPGAs only.
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